Design rules are required in integrated circuit design which allow for variations in the fabrication processes to protect against catastrophic failures and to guarantee the electrical parameters of the devices; the electrical parameters being related to the physical dimensions of the features. Certain feature sizes and minimum space or design tolerance must be maintained between devices in order to maintain the electrical integrity of the devices. Shapes and sizes may vary as a result of, for example, mask misalignment or variations in photoresist exposure. Design rules have thus been established for the various types of material used and the particular location of the devices on the chip, for example, width and spacing rules exist for metal, diffusion and polysilicon materials as well as for contact openings such as a metal contact space to gate. Any misalignment in the formation of a metal contact, for example to a diffused region, may invade the required space between the contact and a surrounding device such as the polysilicon gate. Thus, reduction in the minimum required spacing will not meet the design tolerance and will not insure the devices' electrical characteristics.
To avoid the problems caused by a metal contact when misalignment or other spacing problems occur between, for example, the metal contact and gate, a landing pad may be formed between the metal contact and an underlying diffused region. The landing pad may be formed from a polysilicon layer over which a silicide layer may be formed to decrease sheet resistance. Due to the design rules for polysilicon, the landing pad will allow for a reduction in the size of the cell and tolerate greater misalignment problems. The landing pad, however, creates a topography problem for subsequently formed layers. Depending on the actual layout, the contact opening formed over the landing pad has a higher aspect ratio, the height of the contact opening divided by the width of the opening, than an opening formed without a landing pad. The larger the aspect ratio, the more difficult it will be to fill a contact opening.
An additional problem in the field of integrated circuit manufacture, particularly with the continuing trend toward smaller integrated circuit feature sizes, is the making of high-reliability conductive electrical contacts between metallization layers and semiconductor elements, particularly contacts between aluminum and diffused junctions into single-crystal silicon. This increased difficulty is due to the tendency for aluminum and silicon to interdiffuse when in contact with one another, and when subjected to the high temperatures necessary for integrated circuit manufacturing. As is well known in the art, conventional integrated circuit process steps can cause silicon from the substrate to diffuse rather rapidly into pure aluminum in an attempt to satisfy the solubility of silicon in aluminum. The silicon exiting the substrate is then replaced by the newly formed aluminum+silicon alloy. The diffusion back into the substrate of the aluminum+silicon alloy may diffuse to such a depth as to short out a shallow p-n junction in the silicon. This phenomenon is known as junction spiking. The use of silicon-doped aluminum in forming integrated circuit metallization, while preventing junction spiking, is known to introduce the vulnerability of the contact junction to the formation of silicon nodules thereat, such nodules effectively reducing the contact area, and thus significantly reducing the conductivity of the contact.
Accordingly, recent advances in the field of integrated circuit fabrication have been made by the introduction of so-called "barrier" layers at the aluminum-silicon interface. Conventionally, the barrier layer is a refractory metal material such as titanium-tungsten (TiW), or a refractory metal nitride such as titanium nitride (TiN). The barrier layer is formed at the contact location so as to be disposed between the silicon and the overlying aluminum layer. In some cases, the barrier layer is formed by deposition of the refractory metal, followed by an anneal which forms both the barrier layer and also a metal silicide where the metal is in contact with the silicon; as is known in the art, the metal silicide improves the conductivity of the contact. In any case, the barrier layer inhibits the interdiffusion of aluminum and silicon atoms, thus eliminating the problems of junction spiking and silicon nodule formation noted above.
While a barrier layer eliminates the problems associated with aluminum in direct contact with silicon, it is difficult to form a uniform barrier in contact openings that have a large aspect ratio such as that in contact with a landing pad. Even with today's deposition technology including chemical vapor deposition (CVD) and collimated sputtering, it is often hard to uniformly coat all sides in an opening, particularly in the corners of the openings. If the barrier layer is not thick enough, pin holes may result from inadequate coverage, resulting in the junction spiking problem noted above, to occur.
It is therefore an object of the present invention to provide a method of forming an integrated circuit with a landing pad in such a manner as to reduce the aspect ratio of the metal contact opening.
It is a further object of the present invention to provide such a method that provides more planarization for subsequent processing steps which will improve step coverage of subsequently formed barrier layers and metal contacts.
It is a yet further object of the present invention to provide such a method that provides more planarization by forming a dual polysilicon landing pad over an active area.
It is a further object of the present invention to provide such a method that tolerates misalignment of contact openings over the landing pad.
It is a further object of the present invention to provide such a method that utilizes standard processes.
Other objects and advantages of the present method will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.